1. Field of the Invention
The present invention refers to an integrated device with Schottky diode and MOS transistor and to the related manufacturing process.
2. Relevant Background
The MOS devices are frequently used as synchronous rectifiers, for example in the bridge circuit configurations of the DC/DC converters. A synchronous rectifier acts like a diode: it is turned on when its equivalent diode has to conduct and it is turned off when the equivalent diode has to cease the conduction. The vertical semiconductor MOS devices have an intrinsic diode, which is formed by the junction between the body region and the drain region and which is called “body diode”, that interferes with the operation of the MOS device as a synchronous rectifier. In fact such body diode switches slowly, it has a high conduction voltage and may product electromagnetic radiation emissions in the circuit configurations where the MOS device is inserted.
For reducing the switching time of the body diode technologies for controlling the life time of the minority carriers are presently used which consist of introducing metal, as gold or platinum, inside the MOS device. Such technologies cause a reduction of the life time of the minority carriers, increase the conduction losses and do not decrease the electromagnetic radiation emissions in the circuit configurations where the MOS device is inserted.
Another solution used for reducing the switching time of the body diode consists of arranging a Schottky diode, which has equal voltage and a suitable area, in parallel thereto. The Schottky diode has a fast recovery because minority carriers do not exist and has lower conduction voltage values for the different barrier heights. The combination of the body diode in parallel to the Schottky diode provides for an equivalent structure having a short switching time and a lower conduction voltage.
Discrete component structures are used for the structure made up by the body diode in parallel to the Schottky diode.
An integrated type structure is disclosed in U.S. Pat. No. 5,886,383. In such patent there is the device structure shown in FIG. 1. A MOS device having a polygonal cell structure is formed together with a Schottky diode in a common silicon substrate of N+-type. A N-type epitaxial layer 100 is formed on the said silicon substrate which receives a plurality of P-type regions 41 and 42 which comprise source regions 140 and 150 and which have central openings 44 and 45 through which the region 100 protrudes, so that a metal layer 220 contacts the region 100; in such a way the diode Schottky is formed. In the structure in FIG. 1 each channel region is covered by a gate oxide on which a polysilicon layer 200 is superimposed. Another oxide layer 210 is superimposed on the polysilicon layer for insulating it from the metal layer 220. A drain electrode is applied under the chip 90.
Therefore the Schottky diode in the MOS device in FIG. 1 is formed by interrupting the body regions of the single elementary cells of the device, by forming an alternation of body regions and device substrate portions; said substrate portions are contacted by the metal used for contacting the source regions.
Such solution, even if it is efficacious, gives the problem of the interruption of the body regions in the MOS elementary cells and results unusable in certain cases, as, for example, in MOS devices having multi-drain structures (MD), that is where the body regions extend in depth inside the substrate of the MOS device.